1. Technical Field
The present invention relates generally to integrated circuits and, in particular, to distributed phase detection for clock synchronization in multi-layer 3D stacks.
2. Description of the Related Art
A three-dimensional (3D) stacked chip includes two or more electronic integrated circuit chips (referred to as strata or stratum) stacked one on top of the other. The strata are connected to each other with inter-strata interconnects that could use C4 bump or other technology, and the strata could include through-Silicon vias (TSVs) to connect from the active electronics on one side of the stratum to the opposite side of the stratum. The active electronics can be on the “front” or “back” side of the stratum.
However, the synchronization of a global clock for the stacked chip poses a number of problems. These problems relate to a set of constraints that should be imposed on the synchronization. The set of constraints include, but are not limited to, the following: strata must be testable at the target clock frequency before stacking; inter-stratum and within stratum skews must be small over the entire clock mesh; low power and area overheads; applicable to both grid and non-grid clock networks; and capable of tracking layer-to-layer clock skew due to process, voltage, and temperature variations using a feedback loop.